The baseline feature of this library: declarations for all documented and various undocumented hardware registers. More...

Data Structures
struct	raspi_AUX_regs
	Auxillary peripherals generic configuration. More...

struct	raspi_UART1_regs
	Auxillary mini UART (= UART1). More...

struct	raspi_SPI1_regs
	Auxillary mini SPI 0 (= SPI1). More...

struct	raspi_BSC0_regs
	BSC0 (I2C0) master. More...

struct	raspi_dma_control_block
	DMA control block. More...

struct	raspi_DMA15_regs
	DMA channel 15. More...

struct	raspi_DMA_GLOBAL_regs
	DMA global control. More...

struct	raspi_RNG_regs
	Hardware Random Number Generator. More...

union	raspi_RNG_regs.CTRL

union	raspi_RNG_regs.STATUS

union	raspi_RNG_regs.FF_THRES

union	raspi_RNG_regs.INT_MASK

struct	raspi_EMMC_regs
	External Mass Media Controller (MMC/SD/SDIO). More...

struct	raspi_GPIO_regs
	General-Purpose I/O. More...

struct	raspi_GPCLK_regs
	General Purpose Clock. More...

struct	raspi_GPCLK_regs.CM

struct	raspi_IRQ_regs
	Interrupt Controller. More...

struct	raspi_PCM_regs
	PCM / I2S Audio. More...

union	raspi_PCM_regs.CS

union	raspi_PCM_regs.MODE

union	raspi_PCM_regs.RXC

union	raspi_PCM_regs.TXC

union	raspi_PCM_regs.DREQ

union	raspi_PCM_regs.INTEN

union	raspi_PCM_regs.INTSTC

union	raspi_PCM_regs.GRAY

struct	raspi_PWM_regs
	Pulse Width Modulator. More...

struct	raspi_SPI0_regs
	Serial Peripheral Interface master (SPI0). More...

union	raspi_SPI0_regs.CS

union	raspi_SPI0_regs.CLK

union	raspi_SPI0_regs.DLEN

union	raspi_SPI0_regs.LTOH

union	raspi_SPI0_regs.DC

struct	raspi_BSCSL_regs
	BSC/SPI slave. More...

struct	raspi_ST_regs
	System Timer. More...

union	raspi_ST_regs.CS

struct	raspi_UART0_regs
	ARM UART (UART0). More...

union	raspi_UART0_regs.DR

union	raspi_UART0_regs.RSRECR

union	raspi_UART0_regs.FR

union	raspi_UART0_regs.IBRD

union	raspi_UART0_regs.FBRD

union	raspi_UART0_regs.LCRH

union	raspi_UART0_regs.CR

union	raspi_UART0_regs.IFLS

union	raspi_UART0_regs.IMSC

union	raspi_UART0_regs.RIS

union	raspi_UART0_regs.MIS

union	raspi_UART0_regs.ICR

union	raspi_UART0_regs.ITCR

union	raspi_UART0_regs.ITIP

union	raspi_UART0_regs.ITOP

union	raspi_UART0_regs.TDR

struct	raspi_TIMER_regs
	ARM Timer. More...

struct	raspi_USB_regs
	USB controller. More...

struct	raspi_MMC_regs
	Legacy MMC Controller. More...

struct	raspi_CM_reg
	Clock Management. More...

union	raspi_CM_reg.CTL

union	raspi_CM_reg.DIV

struct	raspi_PM_regs
	Power/Reset Management. More...

union	raspi_PM_regs.RSTC

union	raspi_PM_regs.RSTS

union	raspi_PM_regs.WDOG

struct	raspi_RNG_CTRL_reg.CTRL.B

struct	raspi_RNG_STATUS_reg.STATUS.B

struct	raspi_RNG_FF_THRES_reg.FF_THRES.B

struct	raspi_RNG_INT_MASK_reg.INT_MASK.B

struct	raspi_PCM_CS_reg.CS.B

struct	raspi_PCM_MODE_reg.MODE.B

struct	raspi_PCM_RXC_reg.RXC.B

struct	raspi_PCM_TXC_reg.TXC.B

struct	raspi_PCM_DREQ_reg.DREQ.B

struct	raspi_PCM_INTEN_reg.INTEN.B

struct	raspi_PCM_INTSTC_reg.INTSTC.B

struct	raspi_PCM_GRAY_reg.GRAY.B

struct	raspi_SPI0_CS_reg.CS.B

struct	raspi_SPI0_CLK_reg.CLK.B

struct	raspi_SPI0_DLEN_reg.DLEN.B

struct	raspi_SPI0_LTOH_reg.LTOH.B

struct	raspi_SPI0_DC_reg.DC.B

struct	raspi_ST_CS_reg.CS.B

struct	raspi_UART0_DR_reg.DR.B

struct	raspi_UART0_RSRECR_reg.RSRECR.B

struct	raspi_UART0_FR_reg.FR.B

struct	raspi_UART0_IBRD_reg.IBRD.B

struct	raspi_UART0_FBRD_reg.FBRD.B

struct	raspi_UART0_LCRH_reg.LCRH.B

struct	raspi_UART0_CR_reg.CR.B

struct	raspi_UART0_IFLS_reg.IFLS.B

struct	raspi_UART0_IMSC_reg.IMSC.B

struct	raspi_UART0_RIS_reg.RIS.B

struct	raspi_UART0_MIS_reg.MIS.B

struct	raspi_UART0_ICR_reg.ICR.B

struct	raspi_UART0_ITCR_reg.ITCR.B

struct	raspi_UART0_ITIP_reg.ITIP.B

struct	raspi_UART0_ITOP_reg.ITOP.B

struct	raspi_UART0_TDR_reg.TDR.B

struct	raspi_CM_CTL_reg.CTL.B

struct	raspi_CM_DIV_reg.DIV.B

struct	raspi_PM_RSTC_reg.RSTC.B

struct	raspi_PM_RSTS_reg.RSTS.B

struct	raspi_PM_WDOG_reg.WDOG.B

Macros
#define	AUX_OFFSET 0x215000
	AUX register offset.

#define	UART1_OFFSET 0x215040
	UART1 register offset.

#define	SPI1_OFFSET 0x215080
	SPI1 register offset.

#define	SPI2_OFFSET 0x2150c0
	SPI2 register offset.

#define	BSC0_OFFSET 0x205000
	BSC0 register offset.

#define	BSC1_OFFSET 0x804000
	BSC1 register offset.

#define	BSC2_OFFSET 0x805000
	BSC2 register offset.

#define	DMA15_OFFSET 0xe05000
	DMA 15 register offset.

#define	DMA_OFFSET 0x007000
	DMA 0-14 register offset.

#define	DMA_GLOBAL_OFFSET 0x007fe0
	DMA_GLOBAL register offset.

#define	RNG_OFFSET 0x104000
	RNG register offset.

#define	EMMC_OFFSET 0x300000
	EMMC register offset.

#define	GPIO_OFFSET 0x200000
	GPIO register offset.

#define	GPCLK_OFFSET 0x101070
	GPCLK register offset.

#define	IRQ_OFFSET 0x00b200
	IRQ register offset.

#define	PCM_OFFSET 0x203000
	PCM register offset.

#define	PWM_OFFSET 0x20c000
	PWM register offset.

#define	SPI0_OFFSET 0x204000
	SPI0 register offset.

#define	BSCSL_OFFSET 0x214000
	BSCSL register offset.

#define	ST_OFFSET 0x003000
	ST register offset.

#define	UART0_OFFSET 0x201000
	UART0 register offset.

#define	TIMER_OFFSET 0x00b400
	TIMER register offset.

#define	USB_OFFSET 0x980000
	USB register offset.

#define	MMC_OFFSET 0x202000
	MMC register offset.

#define	CM_PASSWD (0x5a)
	Password for the PASSWD field of various Clock Manager registers.

#define	CM_OFFSET 0x101000
	CM register offset.

#define	PM_PASSWD (0x5a)
	Password for the PASSWD field of various Power Management registers.

#define	PM_OFFSET 0x100000
	PM register offset.

Typedefs
typedef raspi_SPI1_regs	raspi_SPI2_regs
	Auxillary mini SPI1 (= SPI2). More...

typedef raspi_BSC0_regs	raspi_BSC1_regs
	BSC1 (I2C1) master. More...

typedef raspi_BSC0_regs	raspi_BSC2_regs
	BSC2 (I2C2) master. More...

typedef raspi_DMA15_regs	raspi_DMA_regs [15]
	DMA channels 0-14. More...

typedef raspi_CM_reg	raspi_CM_regs [57]
	Clock Manager register array.

Enumerations
enum	raspi_CM_CTL_SRC_t { CM_GND = 0, CM_OSC = 1, CM_PLLA = 4, CM_PLLC = 5, CM_PLLD = 6, CM_HDMI = 7 }
	Clock manager sources.

enum	raspi_CM_reg_t { CM_VPU = 1, CM_H264 = 5, CM_UNK_0x30 = 6, CM_V3D = 7, CM_CAM0_LP = 8, CM_DSI_ESC = 11, CM_DPI = 13, CM_GP0 = 14, CM_GP1 = 15, CM_GP2 = 16, CM_HSM = 17, CM_ISP = 18, CM_PCM = 19, CM_PWM = 20, CM_SLIM = 21, CM_SMI = 22, CM_EMMC = 24, CM_TSENS = 28, CM_TIME = 29, CM_UART = 30, CM_VEC = 31, CM_UNK_0x190 = 50, CM_ARM = 54, CM_UNK_0x1C0 = 56 }
	Known clock manager entries.

enum	raspi_PM_RSTC_WRCFG_t { PM_CLR = 0, PM_SET = 1, PM_FULL_RESET = 2 }
	Possible values for `HW.PM.RSTC.B.WRCFG`.

Detailed Description

The baseline feature of this library: declarations for all documented and various undocumented hardware registers.

The entries in HW are named like the structs listed below, with the raspi_ prefix and _regs suffix removed. raspi_DMA_regs is special, as it is an array. Similarly, the clock manager registers raspi_CM_regs is an array indexed by constants of enum raspi_CM_reg_t.

Declared in raspi/hw.h.

Data Structure Documentation

struct raspi_AUX_regs

Auxillary peripherals generic configuration.

Register names have AUX_ prefix stripped.

No external signals.

Data Fields
uint32_t	IRQ
uint32_t	ENABLES

struct raspi_UART1_regs

Auxillary mini UART (= UART1).

Register names have AUX_MU_ prefix and _REG suffix stripped.

Effectively unusable due to overlap with UART0, which has no usable alternate mapping.

Signal	Mapping 1	Mapping 2	Mapping 3
TxD	GPIO14 Alt5 (P1-08)	GPIO32 Alt5 (nc)	GPIO40 Alt5 (R21)
RxD	GPIO15 Alt5 (P1-10)	GPIO33 Alt5 (nc)	GPIO41 Alt5 (nc)
CTS	GPIO16 Alt5 (D5)	GPIO30 Alt5 (P5-5)	GPIO43 Alt5 (nc)
RTS	GPIO17 Alt5 (P1-11)	GPIO31 Alt5 (P5-6)	GPIO42 Alt5 (nc)

Data Fields
uint32_t	IO
uint32_t	IER
uint32_t	IIR
uint32_t	LCR
uint32_t	MCR
uint32_t	LSR
uint32_t	MSR
uint32_t	SCRATCH
uint32_t	CNTL
uint32_t	STAT
uint32_t	BAUD

struct raspi_SPI1_regs

Auxillary mini SPI 0 (= SPI1).

Register names have AUX_SPI0_ prefix and _REG suffix stripped.

Unusable due to missing connections.

Signal	Mapping 1
SCLK	GPIO21 Alt4 (S5-11)
MOSI	GPIO20 Alt4 (nc)
MISO	GPIO19 Alt4 (nc)
CE0_N	GPIO18 Alt4 (P1-12)
CE1_N	GPIO17 Alt4 (P1-11)
CE2_N	GPIO16 Alt4 (D5)

Data Fields
uint32_t	CNTL0
uint32_t	CNTL1
uint32_t	STAT
uint32_t	maybe_PEEK
uint32_t	IO
uint32_t	PEEK
uint32_t	reserved_0x18[2]
uint32_t	maybe_IO[4]
uint32_t	maybe_TXHOLD[4]

struct raspi_BSC0_regs

BSC0 (I2C0) master.

Standard mapping: S5-13/S5-14.

Signal	Mapping 1	Mapping 2	Mapping 3
SDA	GPIO0 Alt0 (S5-14)	GPIO28 Alt0 (P5-3)	GPIO44 Alt1 (nc)
SCL	GPIO1 Alt0 (S5-13)	GPIO29 Alt0 (P5-4)	GPIO45 Alt1 (R27)

Data Fields
uint32_t	C
uint32_t	S
uint32_t	DLEN
uint32_t	A
uint32_t	FIFO
uint32_t	DIV
uint32_t	DEL
uint32_t	CLKT

struct raspi_dma_control_block

DMA control block.

This data structure is expected at the address written to CONBLK_AD / NEXTCONBK.

Data Fields
uint32_t	TI
uint32_t	SOURCE_AD
uint32_t	DEST_AD
uint32_t	TXFR_LEN
uint32_t	STRIDE
uint32_t	NEXTCONBK
uint32_t	DEBUG
uint32_t	reserved_0x1c

struct raspi_DMA15_regs

DMA channel 15.

No external signals.

Data Fields
uint32_t	CS
uint32_t	CONBLK_AD
raspi_dma_control_block	CB
uint32_t	reserved_0x28[54]

struct raspi_DMA_GLOBAL_regs

DMA global control.

No external signals.

Data Fields
uint32_t	INT_STATUS
uint32_t	reserved_0x04[3]
uint32_t	ENABLE

struct raspi_RNG_regs

Hardware Random Number Generator.

No external signals.

Data Fields
union raspi_RNG_regs	CTRL
union raspi_RNG_regs	STATUS
uint32_t	DATA
union raspi_RNG_regs	FF_THRES
union raspi_RNG_regs	INT_MASK

union raspi_RNG_regs.CTRL

Data Fields
uint32_t	U
CTRL	B

union raspi_RNG_regs.STATUS

Data Fields
uint32_t	U
STATUS	B

union raspi_RNG_regs.FF_THRES

Data Fields
uint32_t	U
FF_THRES	B

union raspi_RNG_regs.INT_MASK

Data Fields
uint32_t	U
INT_MASK	B

struct raspi_EMMC_regs

External Mass Media Controller (MMC/SD/SDIO).

Standard mapping: SD-Card connector.

Signal	Mapping 1	Mapping 2
CARD_DET	GPIO46 Alt0? (SD)	none
CLK	GPIO47 Alt0? (SD)	GPIO22 Alt3? (P1-15)
CMD	GPIO48 Alt0? (SD)	GPIO23 Alt3? (P1-16)
DATA0	GPIO49 Alt0? (SD)	GPIO24 Alt3? (P1-18)
DATA1	GPIO50 Alt0? (SD)	GPIO25 Alt3? (P1-22)
DATA2	GPIO51 Alt0? (SD)	GPIO26 Alt3? (nc)
DATA3	GPIO52 Alt0? (SD)	GPIO27 Alt3? (P1-13)

Data Fields
uint32_t	ARG2
uint32_t	BLKSIZECNT
uint32_t	ARG1
uint32_t	CMDTM
uint32_t	RESP[4]
uint32_t	DATA
uint32_t	STATUS
uint32_t	CONTROL0
uint32_t	CONTROL1
uint32_t	INTERRUPT
uint32_t	IRPT_MASK
uint32_t	IRPT_EN
uint32_t	CONTROL2
uint32_t	reserved_0x40[4]
uint32_t	FORCE_IRPT
uint32_t	reserved_0x54[7]
uint32_t	BOOT_TIMEOUT
uint32_t	DBG_SEL
uint32_t	reserved_0x78[2]
uint32_t	EXRDFIFO_CFG
uint32_t	EXRDFIFO_EN
uint32_t	TUNE_STEP
uint32_t	TUNE_STEP_STD
uint32_t	TUNE_STEP_DDR
uint32_t	reserved_0x94[19]
uint32_t	SPI_INT_SPT
uint32_t	reserved_0xf4[2]
uint32_t	SLOTISR_VER

struct raspi_GPIO_regs

General-Purpose I/O.

P1 pin mapping (main GPIO connector):

3.3V | GPIO2 | GPIO3 | GPIO4      | GND    | GPIO17 | GPIO27 | GPIO22 | 3.3V   | GPIO10 | GPIO9  | GPIO11 | GND
     | SDA1  | SCL1  | GPCLK0/TDI |        |        | TMS    | TRST   |        | MOSI   | MISO   | SCK    |
-------------------------------------------------------------------------------------------------------------------
5V   | 5V    | GND   | GPIO14     | GPIO15 | GPIO18 | GND    | GPIO23 | GPIO24 | GND    | GPIO25 | GPIO8  | GPIO7
     |       |       | TxD        | RxD    | PWM0   |        | RTCK   | TDO    | TCK    |        | CE0_N  | CE1_N

P5 pin mapping (PCM):

5V   | GPIO28 | GPIO30 | GND
     | CLK    | DIN    |
--------------------------------
3.3V | GPIO29 | GPIO31 | GND
     | FS     | DOUT   |

S5 pin mapping (CSI):

GPIO	Pin	Default Function
GPIO21	S5-11	GPIO
GPIO5	S5-12	GPCLK1
GPIO1	S5-13	SCL0
GPIO0	S5-14	SDA0

S6 pin mapping (3.5mm audio):

GPIO	Pin	Default Function
GPIO40	right channel via RC filter	PWM0
GPIO45	left channel via RC filter	PWM1

S8 pin mapping (SD):

GPIO	Pin	Connection
GPIO47	Card Detect	direct
GPIO48	Clock	via 33R
GPIO49	Command	via 33R
GPIO50	Data 0	via 33R
GPIO51	Data 1	via 33R
GPIO52	Data 2	via 33R
GPIO53	Data 3	via 33R

Other GPIOs:

GPIO	Pin
GPIO6	IC3-12
GPIO16	D5
GPIO46	IC1-6

Not connected: 12, 13, 19, 20, 26, 32, 33, 34, 35, 36, 37, 38, 39, 41, 42, 43, 44

Data Fields
uint32_t	FSEL[6]
uint32_t	reserved_0x18
uint32_t	SET[2]
uint32_t	reserved_0x24
uint32_t	CLR[2]
uint32_t	reserved_0x30
uint32_t	LEV[2]
uint32_t	reserved_0x3c
uint32_t	EDS[2]
uint32_t	reserved_0x48
uint32_t	REN[2]
uint32_t	reserved_0x54
uint32_t	FEN[2]
uint32_t	reserved_0x60
uint32_t	HEN[2]
uint32_t	reserved_0x6c
uint32_t	LEN[2]
uint32_t	reserved_0x78
uint32_t	AREN[2]
uint32_t	reserved_0x84
uint32_t	AFEN[2]
uint32_t	reserved_0x90
uint32_t	PUD
uint32_t	PUDCLK[2]
uint32_t	reserved_0xa0[4]
uint32_t	Test

struct raspi_GPCLK_regs

General Purpose Clock.

Standard mapping: GPCLK0 = P1-7, GPCLK1 = S5-12, GPCLK2 = unusable

Signal	Mapping 1	Mapping 2	Mapping 3	Mapping 4
GPCLK0	GPIO4 Alt0 (P1-7)	GPIO20 Alt5 (nc)	GPIO32 Alt0 (nc)	GPIO34 Alt0 (nc)
GPCLK1	GPIO5 Alt0 (S5-12)	GPIO21 Alt5 (nc)	GPIO42 Alt0 (nc)	GPIO44 Alt0 (nc)

GPCLK2 | GPIO6 Alt0 (IC3-12) | GPIO43 Alt0 (nc) | |

Note that there is no GPCLK entry in HW. Use HW.CM[GP0] (or [GP1]/[GP2]) instead.

Data Fields
struct raspi_GPCLK_regs	CM[3]

struct raspi_GPCLK_regs.CM

Data Fields
uint32_t	CTL
uint32_t	DIV

struct raspi_IRQ_regs

Interrupt Controller.

No external signals.

Data Fields
uint32_t	pending_basic
uint32_t	pending[2]
uint32_t	FIQ
uint32_t	enable[2]
uint32_t	enable_basic
uint32_t	disable[2]
uint32_t	disable_basic

struct raspi_PCM_regs

PCM / I2S Audio.

Standard mapping: P5

Signal	Mapping 1	Mapping 2
CLK	GPIO18 Alt0 (P1-12)	GPIO28 Alt2 (P5-3)
FS	GPIO19 Alt0 (nc)	GPIO29 Alt2 (P5-4)
DIN	GPIO20 Alt0 (nc)	GPIO30 Alt2 (P5-5)
DOUT	GPIO21 Alt0 (S5-11)	GPIO31 Alt2 (P5-6)

Data Fields
union raspi_PCM_regs	CS
uint32_t	FIFO
union raspi_PCM_regs	MODE
union raspi_PCM_regs	RXC
union raspi_PCM_regs	TXC
union raspi_PCM_regs	DREQ
union raspi_PCM_regs	INTEN
union raspi_PCM_regs	INTSTC
union raspi_PCM_regs	GRAY

union raspi_PCM_regs.CS

Data Fields
uint32_t	U
CS	B

union raspi_PCM_regs.MODE

Data Fields
uint32_t	U
MODE	B

union raspi_PCM_regs.RXC

Data Fields
uint32_t	U
RXC	B

union raspi_PCM_regs.TXC

Data Fields
uint32_t	U
TXC	B

union raspi_PCM_regs.DREQ

Data Fields
uint32_t	U
DREQ	B

union raspi_PCM_regs.INTEN

Data Fields
uint32_t	U
INTEN	B

union raspi_PCM_regs.INTSTC

Data Fields
uint32_t	U
INTSTC	B

union raspi_PCM_regs.GRAY

Data Fields
uint32_t	U
GRAY	B

struct raspi_PWM_regs

Pulse Width Modulator.

Standard mapping: S6 via RC-filter.

Data Fields
uint32_t	CTL
uint32_t	STA
uint32_t	DMAC
uint32_t	RNG1
uint32_t	DAT1
uint32_t	FIF1
uint32_t	RNG2
uint32_t	DAT2

struct raspi_SPI0_regs

Serial Peripheral Interface master (SPI0).

Standard mapping: P1.

Signal	Mapping 1	Mapping 2
SCLK	GPIO11 Alt0 (P1-23)	GPIO39 Alt0 (nc)
MOSI	GPIO10 Alt0 (P1-19)	GPIO38 Alt0 (nc)
MISO	GPIO9 Alt0 (P1-21)	GPIO37 Alt0 (nc)
CE0_N	GPIO8 Alt0 (P1-24)	GPIO36 Alt0 (nc)
CE1_N	GPIO7 Alt0 (P1-26)	GPIO35 Alt0 (nc)

Data Fields
union raspi_SPI0_regs	CS
uint32_t	FIFO
union raspi_SPI0_regs	CLK
union raspi_SPI0_regs	DLEN
union raspi_SPI0_regs	LTOH
union raspi_SPI0_regs	DC

union raspi_SPI0_regs.CS

Data Fields
uint32_t	U
CS	B

union raspi_SPI0_regs.CLK

Data Fields
uint32_t	U
CLK	B

union raspi_SPI0_regs.DLEN

Data Fields
uint32_t	U
DLEN	B

union raspi_SPI0_regs.LTOH

Data Fields
uint32_t	U
LTOH	B

union raspi_SPI0_regs.DC

Data Fields
uint32_t	U
DC	B

struct raspi_BSCSL_regs

BSC/SPI slave.

Unusable due to missing connections.

Signal	Mapping 1
SCLK/SCL	GPIO19 Alt3 (nc)
MOSI/SDA	GPIO18 Alt3 (P1-12)
MISO	GPIO20 Alt3 (nc)
CE_N	GPIO21 Alt3 (S5-11)

Data Fields
uint32_t	DR
uint32_t	RSR
uint32_t	SLV
uint32_t	CR
uint32_t	FR
uint32_t	IFLS
uint32_t	IMSC
uint32_t	RIS
uint32_t	MIS
uint32_t	ICR
uint32_t	DMACR
uint32_t	TDR
uint32_t	GPUSTAT
uint32_t	HCTRL
uint32_t	DEBUG1
uint32_t	DEBUG2

struct raspi_ST_regs

System Timer.

No external signals.

Data Fields
union raspi_ST_regs	CS
uint32_t	CLO
uint32_t	CHI
uint32_t	C[4]

union raspi_ST_regs.CS

Data Fields
uint32_t	U
CS	B

struct raspi_UART0_regs

ARM UART (UART0).

Standard mapping: P1, no handshake.

Signal	Mapping 1	Mapping 2	Mapping 3
TxD	GPIO14 Alt0 (P1-08)	GPIO32 Alt3 (nc)	GPIO36 Alt2 (nc)
RxD	GPIO15 Alt0 (P1-10)	GPIO33 Alt3 (nc)	GPIO37 Alt2 (nc)
CTS	GPIO16 Alt3 (D5)	GPIO30 Alt3 (P5-5)	GPIO39 Alt2 (nc)
RTS	GPIO17 Alt3 (P1-11)	GPIO31 Alt3 (P5-6)	GPIO38 Alt2 (nc)

Data Fields
union raspi_UART0_regs	DR
union raspi_UART0_regs	RSRECR
uint32_t	reserved_0x08[4]
union raspi_UART0_regs	FR
uint32_t	reserved_0x1c
uint32_t	ILPR
union raspi_UART0_regs	IBRD
union raspi_UART0_regs	FBRD
union raspi_UART0_regs	LCRH
union raspi_UART0_regs	CR
union raspi_UART0_regs	IFLS
union raspi_UART0_regs	IMSC
union raspi_UART0_regs	RIS
union raspi_UART0_regs	MIS
union raspi_UART0_regs	ICR
uint32_t	DMACR
uint32_t	reserved_0x4c[14]
union raspi_UART0_regs	ITCR
union raspi_UART0_regs	ITIP
union raspi_UART0_regs	ITOP
union raspi_UART0_regs	TDR

union raspi_UART0_regs.DR

Data Fields
uint32_t	U
DR	B

union raspi_UART0_regs.RSRECR

Data Fields
uint32_t	U
RSRECR	B

union raspi_UART0_regs.FR

Data Fields
uint32_t	U
FR	B

union raspi_UART0_regs.IBRD

Data Fields
uint32_t	U
IBRD	B

union raspi_UART0_regs.FBRD

Data Fields
uint32_t	U
FBRD	B

union raspi_UART0_regs.LCRH

Data Fields
uint32_t	U
LCRH	B

union raspi_UART0_regs.CR

Data Fields
uint32_t	U
CR	B

union raspi_UART0_regs.IFLS

Data Fields
uint32_t	U
IFLS	B

union raspi_UART0_regs.IMSC

Data Fields
uint32_t	U
IMSC	B

union raspi_UART0_regs.RIS

Data Fields
uint32_t	U
RIS	B

union raspi_UART0_regs.MIS

Data Fields
uint32_t	U
MIS	B

union raspi_UART0_regs.ICR

Data Fields
uint32_t	U
ICR	B

union raspi_UART0_regs.ITCR

Data Fields
uint32_t	U
ITCR	B

union raspi_UART0_regs.ITIP

Data Fields
uint32_t	U
ITIP	B

union raspi_UART0_regs.ITOP

Data Fields
uint32_t	U
ITOP	B

union raspi_UART0_regs.TDR

Data Fields
uint32_t	U
TDR	B

struct raspi_TIMER_regs

ARM Timer.

No external signals.

Data Fields
uint32_t	Load
uint32_t	Value
uint32_t	Control
uint32_t	IRQClearAck
uint32_t	RawIRQ
uint32_t	MaskedIRQ
uint32_t	Reload
uint32_t	Predivider
uint32_t	Freerunning

struct raspi_USB_regs

USB controller.

Uses dedicated pins connected to USB/LAN chip.

Data Fields
uint32_t	unknown[32]
uint32_t	MDIO_CNTL
uint32_t	MDIO_GEN
uint32_t	VBUS_DRV

struct raspi_MMC_regs

Legacy MMC Controller.

Supposedly connected to the same pins as the EMMC.

Data Fields
uint32_t	Command
uint32_t	Argument
uint32_t	Timeout
uint32_t	ClkDiv
uint32_t	Response[4]
uint32_t	Status
uint32_t	Unknown_0x24[3]
uint32_t	VDD
uint32_t	EDM
uint32_t	HostConfig
uint32_t	HBCT
uint32_t	Data
uint32_t	Unknown_0x44[3]
uint32_t	HBLC

struct raspi_CM_reg

Clock Management.

No external connections.

Data Fields
union raspi_CM_reg	CTL
union raspi_CM_reg	DIV

union raspi_CM_reg.CTL

Data Fields
uint32_t	U
CTL	B

union raspi_CM_reg.DIV

Data Fields
uint32_t	U
DIV	B

struct raspi_PM_regs

Power/Reset Management.

No external connections.

Data Fields
uint32_t	unknown_0x00[0x1c]
union raspi_PM_regs	RSTC
union raspi_PM_regs	RSTS
union raspi_PM_regs	WDOG

union raspi_PM_regs.RSTC

Data Fields
uint32_t	U
RSTC	B

union raspi_PM_regs.RSTS

Data Fields
uint32_t	U
RSTS	B

union raspi_PM_regs.WDOG

Data Fields
uint32_t	U
WDOG	B

struct raspi_RNG_regs::raspi_RNG_CTRL_reg.CTRL.B

Data Fields
uint32_t	RBGEN:1
uint32_t	RBG2X:1
uint32_t	reserved:30

struct raspi_RNG_regs::raspi_RNG_STATUS_reg.STATUS.B

Data Fields
uint32_t	WARM_CNT:20
uint32_t	reserved:4
uint32_t	VAL:8

struct raspi_RNG_regs::raspi_RNG_FF_THRES_reg.FF_THRES.B

Data Fields
uint32_t	FF_THRESH:8
uint32_t	reserved:24

struct raspi_RNG_regs::raspi_RNG_INT_MASK_reg.INT_MASK.B

Data Fields
uint32_t	INT_OFF:1
uint32_t	reserved:31

struct raspi_PCM_regs::raspi_PCM_CS_reg.CS.B

Data Fields
uint32_t	EN:1
uint32_t	RXON:1
uint32_t	TXON:1
uint32_t	TXCLR:1
uint32_t	RXCLR:1
uint32_t	TXTHR:2
uint32_t	RXTHR:2
uint32_t	DMAEN:1
uint32_t	reserved0:3
uint32_t	TXSYNC:1
uint32_t	RXSYNC:1
uint32_t	TXERR:1
uint32_t	RXERR:1
uint32_t	TXW:1
uint32_t	RXR:1
uint32_t	TXD:1
uint32_t	RXD:1
uint32_t	TXE:1
uint32_t	RXF:1
uint32_t	RXSEX:1
uint32_t	SYNC:1
uint32_t	STBY:1
uint32_t	reserved1:6

struct raspi_PCM_regs::raspi_PCM_MODE_reg.MODE.B

Data Fields
uint32_t	FSLEN:10
uint32_t	FLEN:10
uint32_t	FSI:1
uint32_t	FSM:1
uint32_t	CLKI:1
uint32_t	CLKM:1
uint32_t	FTXP:1
uint32_t	FRXP:1
uint32_t	PDME:1
uint32_t	PDMN:1
uint32_t	CLK_DIS:1
uint32_t	reserved:3

struct raspi_PCM_regs::raspi_PCM_RXC_reg.RXC.B

Data Fields
uint32_t	CH2WID:4
uint32_t	CH2POS:10
uint32_t	CH2EN:1
uint32_t	CH2WEX:1
uint32_t	CH1WID:4
uint32_t	CH1POS:10
uint32_t	CH1EN:1
uint32_t	CH1WEX:1

struct raspi_PCM_regs::raspi_PCM_TXC_reg.TXC.B

Data Fields
uint32_t	CH2WID:4
uint32_t	CH2POS:10
uint32_t	CH2EN:1
uint32_t	CH2WEX:1
uint32_t	CH1WID:4
uint32_t	CH1POS:10
uint32_t	CH1EN:1
uint32_t	CH1WEX:1

struct raspi_PCM_regs::raspi_PCM_DREQ_reg.DREQ.B

Data Fields
uint32_t	RX:7
uint32_t	reserved0:1
uint32_t	TX:7
uint32_t	reserved1:1
uint32_t	RX_PANIC:7
uint32_t	reserved2:1
uint32_t	TX_PANIC:7
uint32_t	reserved3:1

struct raspi_PCM_regs::raspi_PCM_INTEN_reg.INTEN.B

Data Fields
uint32_t	TXW:1
uint32_t	RXR:1
uint32_t	TXERR:1
uint32_t	RXERR:1
uint32_t	reserved:28

struct raspi_PCM_regs::raspi_PCM_INTSTC_reg.INTSTC.B

Data Fields
uint32_t	TXW:1
uint32_t	RXR:1
uint32_t	TXERR:1
uint32_t	RXERR:1
uint32_t	reserved:28

struct raspi_PCM_regs::raspi_PCM_GRAY_reg.GRAY.B

Data Fields
uint32_t	EN:1
uint32_t	CLR:1
uint32_t	FLUSH:1
uint32_t	reserved0:1
uint32_t	RXLEVEL:6
uint32_t	FLUSHED:6
uint32_t	RXFIFOLEVEL:6
uint32_t	reserved1:10

struct raspi_SPI0_regs::raspi_SPI0_CS_reg.CS.B

Data Fields
uint32_t	CS:2
uint32_t	CPHA:1
uint32_t	CPOL:1
uint32_t	CLEAR:2
uint32_t	CSPOL:1
uint32_t	TA:1
uint32_t	DMAEN:1
uint32_t	INTD:1
uint32_t	INTR:1
uint32_t	ADCS:1
uint32_t	REN:1
uint32_t	LEN:1
uint32_t	LMONO:1
uint32_t	TE_EN:1
uint32_t	DONE:1
uint32_t	RXD:1
uint32_t	TXD:1
uint32_t	RXR:1
uint32_t	RXF:1
uint32_t	CSPOL0:1
uint32_t	CSPOL1:1
uint32_t	CSPOL2:1
uint32_t	DMA_LEN:1
uint32_t	LEN_LONG:1
uint32_t	reserved:6

struct raspi_SPI0_regs::raspi_SPI0_CLK_reg.CLK.B

Data Fields
uint32_t	CDIV:16
uint32_t	reserved:16

struct raspi_SPI0_regs::raspi_SPI0_DLEN_reg.DLEN.B

Data Fields
uint32_t	LEN:16
uint32_t	reserved:16

struct raspi_SPI0_regs::raspi_SPI0_LTOH_reg.LTOH.B

Data Fields
uint32_t	TOH:16
uint32_t	reserved:16

struct raspi_SPI0_regs::raspi_SPI0_DC_reg.DC.B

Data Fields
uint32_t	TDREQ:8
uint32_t	TPANIC:8
uint32_t	RDREQ:8
uint32_t	RDPANIC:8

struct raspi_ST_regs::raspi_ST_CS_reg.CS.B

Data Fields
uint32_t	M0:1
uint32_t	M1:1
uint32_t	M2:1
uint32_t	M3:1
uint32_t	reserved:28

struct raspi_UART0_regs::raspi_UART0_DR_reg.DR.B

Data Fields
uint32_t	DATA:8
uint32_t	FE:1
uint32_t	PE:1
uint32_t	BE:1
uint32_t	OE:1
uint32_t	reserved:20

struct raspi_UART0_regs::raspi_UART0_RSRECR_reg.RSRECR.B

Data Fields
uint32_t	FE:1
uint32_t	PE:1
uint32_t	BE:1
uint32_t	OE:1
uint32_t	reserved:28

struct raspi_UART0_regs::raspi_UART0_FR_reg.FR.B

Data Fields
uint32_t	CTS:1
uint32_t	DSR:1
uint32_t	DCD:1
uint32_t	BUSY:1
uint32_t	RXFE:1
uint32_t	TXFF:1
uint32_t	RXFF:1
uint32_t	TXFE:1
uint32_t	RI:1
uint32_t	reserved:23

struct raspi_UART0_regs::raspi_UART0_IBRD_reg.IBRD.B

Data Fields
uint32_t	IBRD:16
uint32_t	reserved:16

struct raspi_UART0_regs::raspi_UART0_FBRD_reg.FBRD.B

Data Fields
uint32_t	FBRD:6
uint32_t	reserved:26

struct raspi_UART0_regs::raspi_UART0_LCRH_reg.LCRH.B

Data Fields
uint32_t	BRK:1
uint32_t	PEN:1
uint32_t	EPS:1
uint32_t	STP2:1
uint32_t	FEN:1
uint32_t	WLEN:2
uint32_t	SPS:1
uint32_t	reserved:24

struct raspi_UART0_regs::raspi_UART0_CR_reg.CR.B

Data Fields
uint32_t	UARTEN:1
uint32_t	SIREN:1
uint32_t	SIRLP:1
uint32_t	reserved0:4
uint32_t	LBE:1
uint32_t	TXE:1
uint32_t	RXE:1
uint32_t	DTR:1
uint32_t	RTS:1
uint32_t	OUT1:1
uint32_t	OUT2:1
uint32_t	RTSEN:1
uint32_t	CTSEN:1
uint32_t	reserved1:16

struct raspi_UART0_regs::raspi_UART0_IFLS_reg.IFLS.B

Data Fields
uint32_t	TXIFLSEL:3
uint32_t	RXIFLSEL:3
uint32_t	TXIFPSEL:3
uint32_t	RXIFPSEL:3
uint32_t	reserved:20

struct raspi_UART0_regs::raspi_UART0_IMSC_reg.IMSC.B

Data Fields
uint32_t	RIMM:1
uint32_t	CTSMIM:1
uint32_t	DCDMIM:1
uint32_t	DSRMIM:1
uint32_t	RXIM:1
uint32_t	TXIM:1
uint32_t	RTIM:1
uint32_t	FEIM:1
uint32_t	PEIM:1
uint32_t	BEIM:1
uint32_t	OEIM:1
uint32_t	reserved:21

struct raspi_UART0_regs::raspi_UART0_RIS_reg.RIS.B

Data Fields
uint32_t	RIRMIS:1
uint32_t	CTSRMIS:1
uint32_t	DCDRMIS:1
uint32_t	DSRRMIS:1
uint32_t	RXRIS:1
uint32_t	TXRIS:1
uint32_t	RTRIS:1
uint32_t	FERIS:1
uint32_t	PERIS:1
uint32_t	BERIS:1
uint32_t	OERIS:1
uint32_t	reserved:21

struct raspi_UART0_regs::raspi_UART0_MIS_reg.MIS.B

Data Fields
uint32_t	RIMMIS:1
uint32_t	CTSMMIS:1
uint32_t	DCDMMIS:1
uint32_t	DSRMMIS:1
uint32_t	RXMIS:1
uint32_t	TXMIS:1
uint32_t	RTMIS:1
uint32_t	FEMIS:1
uint32_t	PEMIS:1
uint32_t	BEMIS:1
uint32_t	OEMIS:1
uint32_t	reserved:21

struct raspi_UART0_regs::raspi_UART0_ICR_reg.ICR.B

Data Fields
uint32_t	RIMIC:1
uint32_t	CTSMIC:1
uint32_t	DCDMIC:1
uint32_t	DSRMIC:1
uint32_t	RXIC:1
uint32_t	TXIC:1
uint32_t	RTIC:1
uint32_t	FEIC:1
uint32_t	PEIC:1
uint32_t	BEIC:1
uint32_t	OEIC:1
uint32_t	reserved:21

struct raspi_UART0_regs::raspi_UART0_ITCR_reg.ITCR.B

Data Fields
uint32_t	ITCR0:1
uint32_t	ITCR1:1
uint32_t	reserved:30

struct raspi_UART0_regs::raspi_UART0_ITIP_reg.ITIP.B

Data Fields
uint32_t	ITIP0:1
uint32_t	reserved0:2
uint32_t	ITIP3:1
uint32_t	reserved1:28

struct raspi_UART0_regs::raspi_UART0_ITOP_reg.ITOP.B

Data Fields
uint32_t	ITOP0:1
uint32_t	reserved0:2
uint32_t	ITOP3:1
uint32_t	reserved1:2
uint32_t	ITOP6:1
uint32_t	ITOP7:1
uint32_t	ITOP8:1
uint32_t	ITOP9:1
uint32_t	ITOP10:1
uint32_t	ITOP11:1
uint32_t	reserved2:20

struct raspi_UART0_regs::raspi_UART0_TDR_reg.TDR.B

Data Fields
uint32_t	TDR10_0:11
uint32_t	reserved0:21

struct raspi_CM_reg::raspi_CM_CTL_reg.CTL.B

Data Fields
uint32_t	SRC:4
uint32_t	ENAB:1
uint32_t	KILL:1
uint32_t	reserved0:1
uint32_t	BUSY:1
uint32_t	FLIP:1
uint32_t	MASH:2
uint32_t	reserved1:13
uint32_t	PASSWD:8

struct raspi_CM_reg::raspi_CM_DIV_reg.DIV.B

Data Fields
uint32_t	DIVF:12
uint32_t	DIVI:12
uint32_t	PASSWD:8

struct raspi_PM_regs::raspi_PM_RSTC_reg.RSTC.B

Data Fields
uint32_t	reserved0:1
uint32_t	RESET1:1
uint32_t	reserved1:2
uint32_t	WRCFG:2
uint32_t	reserved2:2
uint32_t	RESET2:1
uint32_t	reserved3:15
uint32_t	PASSWD:8

struct raspi_PM_regs::raspi_PM_RSTS_reg.RSTS.B

Data Fields
uint32_t	HADDRQ:1
uint32_t	HADDRF:1
uint32_t	HADDRH:1
uint32_t	reserved0:1
uint32_t	HADWRQ:1
uint32_t	HADWRF:1
uint32_t	HADWRH:1
uint32_t	reserved1:1
uint32_t	HADDSRQ:1
uint32_t	HADDSRF:1
uint32_t	HADDSRH:1
uint32_t	reserved2:1
uint32_t	HADPOR:1
uint32_t	reserved3:19